The present application is related to U.S. patent application Ser. Nos. 06/555,027 now U.S. Pat. No. 4,570,220, and 06/555,028, now abandoned, and hereby refers to, and incorporates by reference the contents of the above-referenced applications.
1. Field of the Invention
The present invention relates to apparatus and methods for transferring data between a source and a plurality of receiving data processing devices using a serial bus with features and characteristics generally found in parallel bus systems. More specifically, the present invention supports multiple master stations with no single point of failure (any agent can be removed or added without failure of the bus), fair and deterministic access, reliable transmission with immediate notification of errors, and a dualistic protocol for intelligent interrupts (short datagram-like packets with low latency) and high throughput for large amounts of data.
2. Art Background
In the computing industry it is quite common to transfer data and commands between a plurality of data processing devices, such as for example, computers, printers, memories, and the like, on a system or data bus. A data processing system typically includes a processor which executes instructions that are stored at addresses in a memory. The data that is processed is transferred into and out of the system by way of input/output (I/O) devices, onto a bus which interconnects the data processing system with other digital hardware. Computer systems constructed with multiple microcomputers fall into two general categories. First, one can create a system with multiple homogeneous processors which can share the computing load dynamically under the control of a single operating system. Second, one can statically partition a computer into modules each with a single processor and a specific function. The functional partitioning allows systems to be constructed of heterogeneous processor and operating systems. The present invention deals with this latter architecture. A key element to the success of a functionally partitioned system is the method of communication between the modules. Functional partitions of a system communicate with one another by sending processed data. The link between the functional partitions can be messages transmitted through a serial or parallel bus.
With the ever increasing capability found in VLSI, the cost of a system will be dominated by the cost of the interconnect between the functional partitions. This cost is proportional to the number of signal wires needed to accomplish the interconnect (60 pins for a typical 32-bit system). The present invention's serial bus permits a low cost implementation because it reduces the signal wire count to just a few wires (2 to 4). If the peripheral devices of a system implement the present invention's serial bus interface, the device controllers which typically convert signals on a prallel system bus to the peripheral I/O bus can be completely eliminated. Thus, the present invention's serial bus considerably reduces the cost of a system.
The present invention's serial bus offers features that are consistent with those offered on a parallel system bus. For example, the present invention permits:
1. A capacity of more than 20 master stations.
2. Deterministic access to the bus for transmission of data.
3. Immediate detection and reporting of errors. Typical prior art serial buses rely on software to detect lost or erroneously received data.
4. Low latency for interrupts.
5. High throughput for transfer of large blocks of data without adversely affecting interrupt latency. For example, memory to memory transfers on the bus do not inhibit the sending of an interrupt for more than a fixed interval.
6. No single point of failure; stations can leave and enter the bus at any time. The present invention's serial bus is intended to be used for key boards, printers, and monitors and these are commonly powered by separate sources.
7. The entire interface and protocol is implementable in a 2 micron CMOS design to allow its inclusion in a micro controller.
Various methods have been devised in order to convey data between a data processing device and a peripheral unit which may be, for example, a memory unit, a second processor unit, a disk drive or the like. For example, in U.S. Pat. No. 4,439,856, issued Mar. 27, 1984, to Ulug, a bus communication system is disclosed having a plurality of bus interface units (BIUs). Each BIU includes a transmission system operable in both a contention mode and a token passing mode. In the contention mode, the transmission system completes the transmission of information packets only after the BIU senses the bus and determines that no additional information packets are being transmitted on the bus. During token passing mode, the transmission system transmits an information packet only after the expiration of a time interval unique to that BIU, and determined by the relative location both of that BIU and of the last BIU to transmit either information or start-up packet on the bus. Accordingly, Ulug discloses a bi-modal operation. This differs from the design of the present invention's high speed serial bus. Ulug defines a method of transfer of information packets only, and does not address a method of acknowledgement. Furthermore, unlike the present invention, the design of Ulug is not decentralized and permits a single point of failure within the network. Ulug requires a dependancy upon adjacent BIUs for token passing, and does not permit fair access to the bus by multiple masters. The transmission speed of Ulug is relatively low. The time is required to support token passing mode is such that the timers are highly likely to get out of skew and are therefore not applicable to high transmission rate systems. As will be described in the present application, the present invention provides acknowledgements at the bus level in the high speed serial bus. The acknowledgements of the present invention are out of band and have no effect on bus performance.
As will be appreciated, the present invention provides a data processing system architecture which includes multiple bus structures in order to optimize data and message transfers between multiple processors, as well as an orderly allocation of system resources to all devices residing on each bus. The present invention's bus structure comprises a general purpose parallel bus, as well as a serial bus which is interconnected through system interfaces which define the communication and data transfer protocols.